Embodiments of the present inventive concepts relate to a semiconductor device, and more particularly, to a clock signal generation circuit for reducing current consumption and a semiconductor device having the same.
Generally, a synchronous semiconductor device is a device synchronized to an external clock signal supplied from outside and operating at a high speed. The synchronous semiconductor device may adjust an operational timing of the synchronous semiconductor device by using the external clock signal, and prevent an error of the synchronous semiconductor device.
The semiconductor device includes a plurality of clock domains. A clock signal generator circuit may generate internal clock signals appropriate to internal circuits of the semiconductor device by using the external clock signal. All signals in a clock domain may be synchronized with an identical clock signal, e.g., an external clock signal.
In addition, when an external clock signal supplied from outside is used in an internal circuit of a synchronous semiconductor device, time delay or clock skew may occur while the external clock signal passes through the internal circuit. The clock signal generation circuit may compensate time delay occurring in the internal circuit by using a replica path modeling a transmission path of an actual clock tree.
Recently, as a semiconductor device is gradually operating at higher speeds, an operational frequency used in the semiconductor device becomes higher and higher and this causes increasing power consumption.